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 FPD200P70
HIGH FREQUENCY PACKAGED PHEMT
FEATURES:
* * * * * * 20 dBm Output Power (P1dB) 17 dB Gain at 5.8 GHz 0.7 dB Noise Figure at 5.8 GHz 30 dBm Output IP3 45% Power-Added Efficiency Useable Gain to 26 GHz
Data sheet v3.0
PACKAGE
RoHS
GENERAL DESCRIPTION:
The FPD200P70 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 mm x 200 mm Schottky barrier Gate, defined by high-resolution stepperbased photolithography.
TYPICAL APPLICATIONS:
* * LNAs and Driver Amplifiers to 26GHz VCOs and Frequency Doublers
TYPICAL PERFORMANCE:
RF PARAMETER
Power at 1dB Gain Compression Small Signal Gain Power-Added Efficiency
SYMBOL
P1dB SSG PAE
CONDITIONS
VDS = 5 V; IDS = 30mA VDS = 5 V; IDS = 30mA VDS = 5 V; IDS = 30mA POUT = P1dB
1.85GHZ
20 21 45
5.8GHZ
19 17 45
18GHZ
20 9 45
UNITS
dBm dB %
Maximum Stable Gain (|S21/S12|) Minimum Noise Figure Output Third-Order Intercept Point POUT = 9 dBm per Tone
MSG NFmin IP3
VDS = 5 V; IDS = 30mA VDS = 5 V; IDS = 30mA VDS = 5V; IDS = 30mA VDS = 8V; IDS = 30mA
24 0.3 29 31
21 0.7 28 30
14 2.2 28.5 31 dB dBm
ELECTRICAL SPECIFICATIONS:
DC PARAMETER
Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes)
SYMBOL
IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| JC
CONDITIONS
VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 0.2 mA IGS = 0.2 mA IGD = 0.2 mA VDS > 3V
MIN
45
TYP
60 120 80 1
MAX
75
UNITS
mA mA mS
10 1.3
A V V V C/W
0.7 12 14.5
0.9 14 16 325
Note: TAMBIENT = 22
1
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FPD200P70
Preliminary Datasheet v3.0
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power 2 VDS VGS IDS IG PIN TCH TSTG PTOT 4
1
SYMBOL
TEST CONDITIONS
-3V < VGS < -0.5V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below 2 or more Max. Limits 8V -3V
ABSOLUTE MAXIMUM
IDSS 5mA 16dBm 175C -40C to 150C 470mW 80%
Channel Operating Temperature Storage Temperature Total Power Dissipation Simultaneous Combination of Limits
Notes: 1 TAmbient = 22C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously 4 Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power Total Power Dissipation to be de-rated as follows above 22C: PTOT= 0.47 - (1/RJC) x TPACK where TPACK= source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C carrier temperature: PTOT = 470mW - (3 x (65 - 22)) = 341mW
BIASING GUIDELINES:
* Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD200P70. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance.
* *
2
Tel: +44 (0) 1325 301111 Preliminary specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com
FPD200P70
Preliminary Datasheet v3.0
TYPICAL FREQUENCY RESPONSE
35 30
FPD200P70 Biased @ 5V, 30mA
MSG S21
FPD200P70 biased @ IDS = 30mA
2.5 2
VD = 5V
MSG
VD = 3V
N.F.min (dB)
25 20 15 10 5 0 0.5 2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26 Frequency (GHz)
1.5 1 0.5 0
Mag S21
&
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0.0% 13
Frequency (GHz)
NOTE: Tuned Noise figure variation against frequency is shown above. The devices were biased nominally at VDS = 5V, IDS = 30mA. The test devices were tuned for minimum noise figure using tuners at the device input and output ports. See Noise Parameter tables for tuned reflection coefficients.
TYPICAL RF PERFORMANCE
Power Transfer Characteristics VDS = 5V, IDS = 30mA at f = 5.8GHz
60.0%
20.0
Pout (dBm) Comp Point
Drain Efficiency and PAE VDS = 5V, IDS = 30mA at f = 5.8GHz
60.0%
8.50
PAE
Eff.
7.50 6.50 5.50 4.50
50.0%
50.0%
Gain Compression (dB)
18.0
Output Power (dBm)
40.0%
40.0%
16.0
14.0 3.50 12.0 2.50 1.50 10.0 0.50 8.0 -7 -5 -3 -1 1 3 5 7 9 11 13 -0.50
30.0%
30.0%
20.0%
20.0%
10.0%
10.0%
0.0% -7 -5 -3 -1 1 3 5 7 9 11
Input Power (dBm)
Input Power (dBm)
Typical Intermodulation Performance VDS = 5V, IDS = 30mA at f = 5.8GHz
13 12 11 10
Output Power (dBm)
Pout (dBm)
-26.00 -28.00
3rds (dBc)
-30.00
3rd Order IM Products (dBc)
-32.00 -34.00 -36.00
9 8
-38.00 7 -40.00 6 5 4 3 2 -11.7 -10.7 -9.7 -8.7 -7.8 -6.8 -5.8 -4.8 -3.8 -42.00 -44.00 -46.00 -48.00 -50.00
NOTE: Typical Power, Efficiency and Intermodulation is shown above. The devices were biased nominally at VDS = 5V, IDS = 30mA at a test frequency of 5.8 GHz. The test devices were tuned using slide tuners at the input and the output ports of the device.
Inpur Power (dBm)
3
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Drain Efficiency (%)
PAE (%)
18
FPD200P70
Preliminary Datasheet v3.0
TEMPERATURE RESPONSE
FPD200P70 Gain & Power Variation over Temperature VDS = 5.0V IDS = 30mA at f = 5.8GHz 19.00 18.00 19.00 18.00 17.00 16.00
28.00 27.00
FPD200P70 IP3 Variation ove r Te mpe rature VDS = 5.0V IDS = 30mA at f = 5.8GHz
Output IP3(dBm)
26.00 25.00 24.00 23.00 22.00 21.00 20.00 -40 -20 0 20 40 60 80
17.00 16.00 15.00
15.00 14.00 13.00 12.00 11.00
P1dB (dBm)
SSG (dB)
OIP3
SSG
14.00 -40 -20 0
P1dB
20 40 60 80
10.00 9.00
Temperature (C)
Temperature (C)
NOTE: Typical power, gain and Intermodulation variation over temperature is shown above. The devices were biased nominally at VDS = 5V, IDS = 30mA at a test frequency of 5.8 GHz on eval board. The eval board is tuned for minimum noise and maximum gain. The 1dB compression point is lower than the typical number due to the change in matching.
TYPICAL I-V CHARACTERISTICS
110
FPD200P70 I-V Curves
110 VG=+0.50V 100 90 80 70 VG=+0.25V
VG=0V
ID (mA)
60 50 40 VG=-0.50V 30 20 10 0 0 VG=-0.75V VG=-0.25V
0.5
1
1.5
2
2.5
3
3.5
VDS (V)
Note: The recommended method for measuring IDSS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above).
4
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FPD200P70
Preliminary Datasheet v3.0
NOISE PARAMETERS
Biased at 5V, 30mA
Freq (GHz) 0.800 0.900 1.000 1.500 1.800 2.000 2.200 2.400 2.600 2.800 3.300 3.500 3.700 4.000 4.500 4.900 5.100 5.300 5.500 5.700 5.900 7.000 8.000 9.000 10.000 11.000 12.000 13.000 14.000 15.000
Biased at 3V, 30mA
Rn/50 Angle 10.9 12.1 13.2 19.1 22.6 24.9 27.2 29.6 31.9 34.2 39.9 42.2 44.5 47.9 53.5 58.0 60.2 62.4 64.7 66.9 69.1 78.6 90.8 97.7 108.3 109.7 127.3 -152.8 -76.9 -41.0 0.454 0.443 0.433 0.386 0.362 0.347 0.334 0.321 0.310 0.300 0.280 0.274 0.269 0.263 0.257 0.255 0.255 0.255 0.255 0.255 0.256 0.214 0.177 0.171 0.161 0.158 0.147 0.174 0.216 0.290 Freq (GHz) 0.800 0.900 1.000 1.500 1.800 2.000 2.200 2.400 2.600 2.800 3.300 3.500 3.700 4.000 4.500 4.900 5.100 5.300 5.500 5.700 5.900 7.000 8.000 9.000 10.000 11.000 12.000 13.000 14.000 15.000
opt
Mag. 0.788 0.788 0.788 0.787 0.784 0.782 0.778 0.774 0.769 0.763 0.746 0.738 0.730 0.715 0.688 0.662 0.649 0.634 0.619 0.604 0.587 0.470 0.367 0.281 0.239 0.185 0.124 0.031 0.118 0.244
opt
Mag. 0.795 0.782 0.769 0.708 0.675 0.654 0.634 0.615 0.598 0.581 0.544 0.531 0.519 0.504 0.483 0.470 0.466 0.463 0.460 0.459 0.459 0.455 0.355 0.267 0.222 0.164 0.103 0.043 0.129 0.249 Angle 12.2 13.5 14.8 21.2 25.0 27.6 30.1 32.7 35.2 37.7 43.9 46.4 48.9 52.6 58.7 63.6 66.0 68.4 70.8 73.2 75.6 81.4 94.7 102.9 114.1 116.6 138.1 -128.1 -72.4 -36.9
Rn/50 0.356 0.352 0.349 0.330 0.320 0.313 0.307 0.301 0.295 0.290 0.277 0.273 0.268 0.262 0.253 0.247 0.245 0.242 0.240 0.237 0.235 0.202 0.167 0.161 0.154 0.153 0.147 0.176 0.223 0.300
5
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FPD200P70
Preliminary Datasheet v3.0
REFERENCE DESIGN 5.15 TO 5.8 GHZ
FREQUENCY
Gain N.F. P1dB IP3 Vd Vg Id
GHZ
dB dB dBm dBm V V mA 17 1.0
5.5
20 15 10
FPD200P70 Bias 5V, 30mA
DB(|S(2,1)|) DB(|S(1,1)|) DB(|S(2,2)|)
Gain and R.L. (dB)
16.5 28 5 -0.4 to -0.6 30
5 0 -5 -10 -15 -20 -25
Board Material is Rogers 4003 with a die electric thickness of 20mil & 1/2 oz. Cu cladding on both sides.
-30 2 2.5 3 3.5 4 4.5 5 5.5 Frequency (GHz) 6 6.5 7 7.5 8
Measured Evaluation board gain and return Loss
SCHEMATIC
MTEE ID=TL11 W1=45 mil W2=90 mil W3=45 mil
1 2 3
CAP ID=C2 C=33 pF PORT P=1 Z=50 Ohm
MLIN ID=TL2 W=90 mil L=420 mil
MTEE ID=TL10 W1=90 mil W2=30 mil W3=45 mil
1 3 2
MLIN ID=TL3 W=30 mil L=150 mil
1
MLIN ID=TL20 W=65 mil L=130 mil
2
MTEE ID=TL23 W1=170 mil W2=65 mil W3=220 mil
2 3 1
MLIN ID=TL18 W=170 mil L=135 mil
MTEE ID=TL22 W1=170 mil W2=45 mil W3=45 mil
1 3 2
MLIN ID=TL14 W=45 mil L=50 mil
CAP ID=C4 C=33 pF PORT P=2 Z=50 Ohm
SUBCKT ID=Q1 NET="FET" MLEF ID=TL12 W=220 mil L=380 mil
RES ID=R1 R=20 Ohm
MLIN ID=TL8 W=45 mil L=30 mil MLIN ID=TL6 W=5 mil L=250 mil MLIN ID=TL5 W=50 mil L=100 mil DCVS ID=V1 V=-0.5 V
MLEF ID=TL1 W=45 mil L=190 mil
MLIN ID=TL17 W=5 mil L=310 mil CAP ID=C5 C=33 pF
MRSTUB2 ID=TL9 Ri=20 mil Ro=350 mil Theta=90 Deg CAP ID=C1 C=33 pF
MRSTUB2 ID=TL21 Ri=20 mil Ro=290 mil Theta=90 Deg MLIN ID=TL15 W=50 mil L=100 mil MLIN ID=TL16 W=50 mil L=50 mil DCVS ID=V2 V=5 V
CAP ID=C6 C=1e6 pF
BOARD LAYOUT
33pF 20 Ohms
Q1
Q1
33pF
P1
33pF 33pF 0.01uF 0.01uF
P2
1.0uF
1.0uF
6
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FPD200P70
Preliminary Datasheet v3.0
P70 PACKAGE OUTLINE AND RECOMMENDED PC BOARD LAYOUT
TAPE AND REEL DIMENSIONS AND PART ORIENTATION
Product Marking The device is marked ABC where :A = Product type B = Week code C = Year code
Terminal tape = 40mm(min.) Leader tape with empty Cavities = 350mm(min.) Trailer tape with empty Cavities = 160mm(min.) Devices per reel = 1000
7
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FPD200P70
Preliminary Datasheet v3.0
S-PARAMETERS BIASED @ 5V, 30MA
FREQ[GHz] 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 6.500 7.000 7.500 8.000 8.500 9.000 9.500 10.000 10.500 11.000 11.500 12.000 12.500 13.000 13.500 14.000 14.500 15.000 15.500 16.000 16.500 17.000 17.500 18.000 18.500 19.000 19.500 20.000 20.500 21.000 21.500 22.000 22.500 23.000 23.500 24.000 24.500 25.000 25.500 26.000 S11m 0.987 0.967 0.936 0.899 0.857 0.817 0.771 0.735 0.701 0.663 0.628 0.594 0.555 0.516 0.471 0.433 0.395 0.366 0.350 0.338 0.324 0.322 0.334 0.360 0.391 0.425 0.457 0.491 0.530 0.561 0.588 0.597 0.611 0.634 0.660 0.683 0.688 0.673 0.656 0.646 0.641 0.647 0.661 0.672 0.669 0.670 0.653 0.643 0.610 0.586 0.555 0.559 S11a -11.6 -23.7 -35.7 -47.8 -59.3 -69.5 -78.3 -86.1 -93.5 -101.3 -109.1 -118.6 -128.1 -139.0 -150.7 -161.4 -171.5 -179.6 173.1 163.1 151.4 136.9 121.1 106.5 94.3 84.5 75.2 66.5 57.1 47.5 37.8 29.2 21.1 12.5 4.7 -1.5 -4.7 -6.5 -8.0 -13.5 -22.8 -33.9 -43.2 -50.7 -57.0 -62.2 -69.2 -77.0 -81.0 -86.1 -92.5 -105.7 S21m 6.94 6.814 6.601 6.334 6.004 5.66 5.318 5.048 4.814 4.612 4.467 4.374 4.268 4.166 4.016 3.869 3.699 3.561 3.511 3.499 3.496 3.478 3.437 3.385 3.331 3.268 3.19 3.108 3.01 2.924 2.852 2.797 2.736 2.672 2.578 2.455 2.307 2.173 2.056 1.987 1.929 1.882 1.839 1.788 1.722 1.647 1.594 1.56 1.538 1.553 1.586 1.612 S21a 167.7 156.2 144.9 133.9 123.4 113.8 104.9 96.8 89.1 81.5 74.2 66.0 58.1 49.8 41.5 33.8 26.3 19.6 13.7 6.6 -0.8 -8.9 -17.1 -25.4 -33.8 -42.5 -51.5 -60.2 -68.7 -76.9 -85.0 -93.4 -102.1 -111.1 -120.4 -129.5 -137.5 -144.8 -151.9 -158.5 -166.0 -174.5 176.4 166.3 156.4 147.6 140.0 131.3 123.8 115.8 107.4 96.8 S12m 0.007 0.013 0.019 0.023 0.027 0.029 0.031 0.031 0.032 0.032 0.032 0.033 0.034 0.036 0.036 0.034 0.031 0.029 0.032 0.039 0.046 0.054 0.061 0.067 0.072 0.078 0.082 0.085 0.088 0.091 0.094 0.095 0.097 0.102 0.101 0.099 0.096 0.093 0.090 0.090 0.089 0.089 0.088 0.089 0.088 0.088 0.087 0.090 0.089 0.096 0.103 0.110 S12a 81.9 75.2 67.9 60.9 54.6 48.8 42.5 38.9 37.6 33.7 32.2 31.0 28.8 23.8 16.5 13.7 11.4 17.8 26.8 27.7 26.7 22.8 16.8 11.0 5.2 -0.9 -7.1 -13.0 -19.7 -24.9 -31.0 -37.5 -42.9 -50.7 -58.3 -65.8 -72.3 -78.1 -84.1 -91.2 -98.8 -106.4 -115.1 -124.1 -133.9 -140.9 -151.0 -157.1 -166.0 -175.0 175.2 165.6 S22m 0.785 0.777 0.765 0.750 0.734 0.718 0.701 0.691 0.683 0.668 0.663 0.656 0.644 0.627 0.600 0.580 0.561 0.557 0.571 0.585 0.601 0.603 0.589 0.575 0.568 0.571 0.575 0.578 0.569 0.559 0.557 0.569 0.576 0.574 0.572 0.577 0.593 0.611 0.623 0.634 0.639 0.640 0.623 0.610 0.608 0.611 0.617 0.610 0.602 0.586 0.561 0.527 S22a -7.3 -14.5 -21.1 -27.1 -32.3 -37.6 -42.5 -47.2 -51.4 -55.2 -58.3 -63.4 -67.9 -73.1 -78.4 -82.7 -87.4 -91.7 -96.1 -102.2 -108.3 -115.7 -123.4 -131.2 -139.5 -149.0 -158.9 -168.4 -177.0 175.2 167.7 157.6 146.2 134.2 122.2 109.8 98.4 88.2 79.9 75.9 73.7 69.8 60.8 47.9 34.5 23.5 15.6 7.1 -1.1 -8.5 -13.3 -21.0
8
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FPD200P70
Preliminary Datasheet v3.0
PREFERRED ASSEMBLY INSTRUCTIONS:
This package is compatible with both lead free and leaded solder reflow processes as defined within IPC/JEDEC J-STD-020C. The maximum package temperature should not exceed 260C. Package leads are gold plated.
ORDERING INFORMATION:
PART NUMBER
FPD200P70 EB200P70-AJ
DESCRIPTION
Packaged pHEMT 5.15 to 5.8GHz evaluation board
HANDLING PRECAUTIONS:
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing.
ESD/MSL RATING:
These devices should be treated as Class 0 (0V - 250V) using the human body model as defined in JEDEC Standard No. 22-A114. The device has a MSL rating of Level 1. To determine this rating, preconditioning was performed to the device per, the Pb-free solder profile defined within IPC/JEDEC J-STD-020C, Moisture / Reflow sensitivity classification for non-hermetic solid state surface mount devices
APPLICATION NOTES & DESIGN DATA:
Application Notes and design data including Sparameters, noise parameters and device model are available on request.
RELIABILITY:
A MTTF of 4.2 million hours at a channel temperature of 150C is achieved for the process used to manufacture this device.
DISCLAIMERS:
This product is not designed for use in any space based or life sustaining/supporting equipment.
9
Tel: +44 (0) 1325 301111 Preliminary specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Website: www.filtronic.com


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